The circuit diagram and truth table is shown below.Ī clock pulse is given to the inputs of the AND Gate. This problem can be overcome by using a bistable SR flip-flop that can change outputs when certain invalid states are met, regardless of the condition of either the Set or the Reset inputs.įor this, a clocked S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop. The problems with S-R flip flops using NOR and NAND gate is the invalid state. If both the values of S and R are switched to 1, then the circuit remembers the value of S and R in their previous state. They are supposed to be compliments of each other. If both the values of S and R are switched to 0 it is an invalid state because the values of both Q and Q’ are 1. In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the compliment value of S.
Like the NOR Gate S-R flip flop, this one also has four states. The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.įig.2 SR Flip-flop Using Nand gates Operation This is an invalid state because the values of both Q and Q’ are 0. If both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their previous state. In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the value of S. Fig.1 SR Flip-flop Using NOR gates Operationįrom the diagram it is evident that the flip flop has mainly four states.